Compilation for Future Nanocomputer Architectures

Compilation has a long history of translating a programmer’s human-readable code into machine instructions designed to make good use of a specific target computer. In this paper, we formalize a compiler framework that broadly defines the task of compilation to include output of a machine description customized to the input program which would be used to generate the target computer. The compiled program would then run on the generated computer. Inspired by research in design space exploration, this compilation approach exploits the proposed capabilities of nanocomputers, which are in the class of reconfigurable parallel architectures. This emerging hardware technology relies on molecular level fabricated circuit design to minimize feature size while creating a vast matrix of reconfigurable processing units, an application of the advancing field of nanotechnology. We identify design issues and present preliminary results that support earlier work in this area and propose future directions.